Clock Tree Synthesis for Timing Convergence and Timing Yield Improvement in Nanometer Technologies

Designing high-performance very large-scale integration (VLSI) chips has become more challenging than ever due to nanometer effects and accelerating time-to-market cycles. Due to the interconnect delay dominance, a small routing change in the design can increase coupling capacitances on its neighboring paths and significantly increase their path delays. This can cause new timing violations and result in design iterations. While timing convergence is getting harder and harder to achieve, the accelerating time-to-market cycles further aggravate the problem. Process variations result in interconnect variations, threshold voltage variations, leakage power variations, etc. These effects not only generate reliability issues but also make the circuit performance deviate from the design specification and cause timing yield losses. Due to the increasing process variations in nanometer technologies, timing yield has become an important design concern because it directly affects the manufacturing cost. Clock designs have significant impacts on both timing convergence and timing yield. A carefully designed clock distribution network can reduce design-inherited clock skews, the discrepancies between designer intended clock skews and achieved clock skews under perfect process conditions. This can improve circuit performance and timing convergence. A clock distribution network can also be optimized to reduce process-induced clock skews, such that the circuit would require less timing margin to tolerate process related timing variations. This will also improve timing convergence and timing yield. Clock